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| PJCLAMP0504A QUAD TVS/ZENER ARRAY FOR ESD AND LATCH-UP PROTECTION This Quad TVS/Zener Array has been designed to Protect Sensitive Equipment against ESD and to prevent Latch-Up events in CMOS circuitry operating at 5Vdc and below. This TVS array offers an integrated solution to protect up to four data lines where the board space is a premium. 6 5 4 PRELIMINARY SPECIFICATION FEATURES 100W Power Dissipation (8/20s Waveform) Low Leakage Current, Maximum of 0.5A @ 5Vdc Very Low Clamping Voltage, Max of 10V @ 9Apk 8/20s IEC61000-4-2 ESD 20kV air, 15kV Contact Compliance Max off state Capacitance of 90pF @ 0Vdc 1 MHz New SMT package QFN 1.6mm x 1.6mm; Max Height of 0.75mm Same Footprint compared to the SOT666 or EIAJ SC-89 1 2 3 6 5 4 1 2 3 APPLICATIONS Personal Digital Assistant (PDA) SIM Card Port Protection (Mobile Phone) Portable Instrumentation Mobile Phones and Accessories Memory Card Port Protection 2 3 1 QFN 2X2 6 5 4 QFN 1.6x1.6 sq mm Package MAXIMUM RATINGS (Per Device) Rating Peak Pulse Power (8/20s Waveform) Peak Pulse Current (8/20s Waveform) ESD Voltage (HBM) Operating Temperature Range Storage Temperature Range Symbol P pp I pp V ESD TJ Tstg Value 100 10 >25 -55 to +150 -55 to + 150 Units W A kV C C ELECTRICAL CHARACTERISTICS (Per Device) Tj = 25C Parameter Reverse Stand-Off Voltage Reverse Breakdown Voltage Reverse Leakage Current Clamping Voltage (8/20s) Clamping Voltage (8/20s) Off State Junction Capacitance Off State Junction Capacitance Symbol VWRM VBR IR Vc Vc Cj Cj I BR = 1 mA VR = 5V I pp = 5A I pp = 9A 0 Vdc Bias f = 1MHz Between I/O pins and pin 2 5 Vdc Bias f = 1MHz Between I/O pins and pin 2 Conditions Min Typical Max 5 Units V V A V V pF pF 6 7.2 0.5 9 10 90 45 12/6/2005 Page 1 www.panjit.com PJCLAMP0504A TYPICAL CHARACTERISTICS 25C unless otherwise noted Capacitance, pF Ipp, Amps Current, A PRELIMINARY Non-Repetitive Peak Pulse Power vs Pulse Time 1000 Peak Pulse Power - Ppp (W) Pulse Waveform 110 100 90 80 70 60 50 40 30 20 10 0 0 100 Percent of Ipp 50% of Ipp @ 20s R tim 10-90% - 8s ise e 10 1 10 100 1000 Pulse Duration, sec 5 10 15 20 25 30 time, sec Capacitance vs. Biasing Voltage @1MHz Clamping Voltage vs Ipp 8x20sec Surge 100 10 9 8 7 6 5 4 3 2 1 0 6 7 8 9 10 11 Clamping Voltage, V 90 80 70 60 50 40 30 0 1 2 3 4 5 Bias Voltage, Vdc Typical Leakage Current vs Temperature 0.1000 0.0100 5V 0.0010 3V 0.0001 25 50 75 Temp,C 100 125 150 12/6/2005 Page 2 www.panjit.com PJCLAMP0504A TYPICAL APPLICATION EXAMPLE PRELIMINARY 12/6/2005 1 2 3 4 Page 3 www.panjit.com PJCLAMP0504A PACKAGE DIMENSIONS AND SUGGESTED BOND PAD LAYOUT TOP VIEW BOTTOM VIEW 0.50 0.05 mm 1.60 0.05 mm 0.20 0.05 mm 0.20 0.05 mm 1.1 0.05 mm 1.60 0.05 mm 0.6 0.05 mm SIDE VIEW 0.203 0.05 mm 0.75 0.05 mm PREFERRED 0.25 0.05 mm ALTERNATE 0.25 0.05 mm 0.40 0.05 mm 0.40 0.05 mm 0.90 0.05 mm 0.55 mm 1.0 0.05 mm 0.50 0.05 mm 1.00 0.05 mm 0.50 0.05 mm 12/6/2005 Page 4 www.panjit.com |
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